Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have found a wide application as electronic devices. They find significant use, for example, in digital processing applications. MOSFETS, like other transistor devices, continue to be scaled to smaller and smaller dimensions in order to improve integrated circuit performance and cost. As the MOSFET device is further miniaturized, however, it becomes increasingly difficult to maintain high performance characteristics. It also becomes increasingly technically challenging to fabricate the MOSFET features in the needed smaller dimensions.
The double gate MOSFET is considered an attractive device to succeed the planar MOSFET structure. With two gates controlling the channel, short-channel effects can be advantageously controlled. The FinFET structure, a kind of semiconductor such as a double gate MOSFET structure, consists of a channel formed in a vertical silicon fin that is controlled by a double gate. It is anticipated that the FinFET design will find good application in the technology node where gate length is approximately 45 to 50 nm, and correspondingly the desired silicon fin width will be approximately half, on the order of 20 nm. In the design and fabrication of FinFET devices it is desired to create a very tall and thin silicon structure. The measurement of such a structure may be characterized by its aspect ratio which is the height/width. An aspect ratio of 4 to 5 would be desired in some examples.
Previously the formation of thin fin structures (approximately 20 nm in width) from an SOI (semiconductor on insulator) structure has been problematic. In the first place the width of the fin structure is beyond the resolution limit or capabilities using the lithographic techniques currently available. Thus, fabrication methods different from the standard lithographic technique must be utilized. These other techniques, generally involving forming a larger silicon structure than desired for the final size, and then trimming the structure dimension through various means to the desired measure, have drawbacks that render them unacceptable.
One such method of trimming oversize silicon fins involves an RIE (reactive ion etch) technique to trim down the silicon fin from its originally overdefined size. This method, however, is limited by manufacturing considerations to creating fins that are not less than approximately 30 nm in width. Thus, the technique is not viable for technology nodes going below that dimension. RIE is also an undesirable technique in that it generates fin structures with surface roughness. Surface roughness leads to poor electrical performance in the finished transistor. Further, RIE methods have poor dimensional control in the wafer method of manufacture; this drawback results in nonuniformity between transistors at different points on a wafer. Thus, RIE is an undesirable method of manufacturing.
Another possible technique is the thinning of a silicon fin through oxidation of the fin structure followed by removal of the SiO2 that results during oxidation. Prior art methods have taught that one can decrease the width of a silicon fin by exposing the fin to oxygen at a reaction promoting temperature. The oxygen thereupon oxidizes the silicon and converts to silicon dioxide. (The silicon dioxide is later removed using other methods such as wet etching.) However, there is an inherent drawback to this process that renders this method undesirable. The process promotes weakness at the point where the silicon fin meets the silicon dioxide substrate layer, the base portion of the fin. This arises by virtue of the fact that there is stress at the interface between the silicon fin structure and the underlying silicon dioxide layer. Upon exposure to oxygen, this stress promotes a preferential reaction of the silicon in the stressed interfacial region with oxygen. Thus there tends to be a greater level of reaction of silicon in the base area. This phenomenon is called necking in view of the problem that arises in the base region where the fin contacts the SiO2 substrate layer. Necking results in a mechanical weakening of the fin; and this weakness leads to problems during the subsequent processing steps that take place in industrial fabrication methods. Further, the narrowing of the fin affects the electrical characteristics of the fin. Hence a pure oxidation is an unattractive method for shaping a fin to a desired dimension.
Still, a timed oxidation is much more controllable than a timed ion etch. Oxidation processes are well characterized and widely practiced in chip manufacturing. Oxidation steps usually do not suffer from the chip-to-chip variability that occurs with a plasma etch process. Thus, it would be desirable to find a fabrication method that takes advantage of the controllability aspect of the oxidation process while eliminating its disadvantages.
Hence there is a need to develop a new method for the fabrication of thin fin structures of silicon. It would be desired that the method yield improved results over prior art methods. It is desired that the resulting fins demonstrate good physical integrity and electrical properties. Further it would be desired that the method be adaptable to present MOSFET processing techniques and apparatus and that it be relatively inexpensive to use. It would further be advantageous if the new method employed existing processing hardware and equipment that is used in semiconductor manufacturing processes. The present invention addresses one or more of these needs.